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Description: 此文档为采用FPGA实现的以太网MAC层，以及嵌入式的TCP/IP协议栈-this document for the introduction of FPGA Ethernet MAC layer, as well as embedded TCP / IP protocol stack
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Size: 1200120 |
Author: 刘荣鑫 |
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Description: 其中两个项目自己做的：一个是雷达模拟跟踪，基于FPGA/CPLD的，里面包含了PCB和VHDL码，还有一个是SDIO的驱动程序（包括PCB原理图，SDIO协议方面的资料还有就是源码，这项目可用），还有一些嵌入式方面的资料，如TCP/IP协议栈的实现，FPGA的一些仿真实例
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Size: 6978765 |
Author: 肖寒 |
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Description: 成功移植于xilinx virtex6下面的LWIP协议栈，成功实现1G以太网TCP/UDP，UDP下实际测试数据传输率可打到900Mbps以上
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Size: 953025 |
Author: taohonggang@gmail.com |
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Description: 此文档为采用FPGA实现的以太网MAC层，以及嵌入式的TCP/IP协议栈-this document for the introduction of FPGA Ethernet MAC layer, as well as embedded TCP/IP protocol stack
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Size: 1200128 |
Author: 刘荣鑫 |
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Description: 其中两个项目自己做的：一个是雷达模拟跟踪，基于FPGA/CPLD的，里面包含了PCB和VHDL码，还有一个是SDIO的驱动程序（包括PCB原理图，SDIO协议方面的资料还有就是源码，这项目可用），还有一些嵌入式方面的资料，如TCP/IP协议栈的实现，FPGA的一些仿真实例-Two of the projects themselves to do: a tracking radar simulator is based on FPGA/CPLD
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Size: 6978560 |
Author: 肖寒 |
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Description: fpga design, give you a brief idea or concept of how the network functions-ethernet basic concept, from osi 7 layer to tcp ip, easy to learn network technology in a single step!
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Size: 947200 |
Author: aichixigua |
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Description: VHDL IP Stack: This IP stack for an FPGA is a complex design because of the number of layers and the complexity of each that is required. It is limited to 10Mb/s operation and is designed for a full duplex switched network. It implements the lower layers of a standard TCP/IP stack. Further implementation is needed to make it work specifically for a certain purpose (eg a web server). There is support to read and write to RAM from the PC via the parallel port as well, for debugging and tests purposes (this maybe easily removed). Note the design only supports IP and ARP frames, other protocols such as RARP and 802.2 frames are not supported.-VHDL IP Stack: This IP stack for an FPGA is a complex design because of the number of layers and the complexity of each that is required. It is limited to 10Mb/s operation and is designed for a full duplex switched network. It implements the lower layers of a standard TCP/IP stack. Further implementation is needed to make it work specifically for a certain purpose (eg a web server). There is support to read and write to RAM from the PC via the parallel port as well, for debugging and tests purposes (this maybe easily removed). Note the design only supports IP and ARP frames, other protocols such as RARP and 802.2 frames are not supported.
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Size: 81920 |
Author: James |
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Description: 辛辛苦苦找到的UDP的资料，在verilog中UDP指的是用户定义的原语。比如说大家有时候会见到“primitive...table...endtable...endendprimitive”这样的代码段，在书上只能找到大概的解释。到网上查的话又老是跟TCP/IP的UDP冲突。所以特地搜集到了这个东西，希望能帮助大家解决“用户原语”相关的问题。-UDP hard to find the information in verilog in the UDP refers to the user-defined primitives. For example, we sometimes see the " primitive ... table ... endtable ... endendprimitive" This code segment can only be found in the book about interpretation. The online search, then they are always with the TCP/IP, UDP conflict. So, specifically to collect this stuff, hoping to help people solve the " user of the original language" related issues.
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Size: 125952 |
Author: 龙也 |
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Description: this a programme about dsp ,it can achieve tcp/ip
communication ,the programme is corect ,i wish that
you can download it .-this is a programme about dsp ,it can achieve tcp/ip
communication ,the programme is corect ,i wish that
you can download it .
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Size: 75776 |
Author: 小龙 |
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Description: ucosii 上实现tcp服务器.通过fpga上移植ip核桃\,实现tcpip的协议，同时实现服务器功能-ucosii to achieve tcp server. fpga on the transplant by ip Walnut \, to achieve tcpip protocol, while the server features to achieve
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Size: 697344 |
Author: 刘裕 |
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Description: FPGA based project which uses TCP/ip stack
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Size: 1020928 |
Author: mehmood |
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Description: Features single-chip GigE hardware TCP/IP Offload Engine that delivers a data rate
of over 100MBytes/s in each direction and a user programmable companion FPGA
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Size: 211968 |
Author: NIK |
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Description: 用verilog实现的UDP协议，包括arp，udp，ip分段协议等，对于想用FPGA实现TCP/IP协议的人来说，应该会起到一定的帮助作用-Implemented with verilog UDP protocols, including arp, udp, ip fragmentation protocol, etc., who want to achieve TCP/IP protocol with the FPGA people, should play a helpful role
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Size: 17408 |
Author: 王江 |
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Description: 基 于 f p g a 的Marvell 88E1111 以 太 网 控 制 器 的 设 计，能发送接收，通过GMII接口实现TCP/UDP 传输-Base on fpga Marvell 88E1111 to mt net control device design, can send and receive, through GMII TCP/UDP transmission on the interface
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Size: 2291712 |
Author: KID |
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Description: Example Project on how to communicate PC to FPGA using UDP/TCP packets-Example Project on how to communicate PC to FPGA using UDP/TCP packets
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Size: 187392 |
Author: nribeiro |
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Description: Xilinx虚拟连接，这是一种基于TCP/IP协议的通信技术，以实现JTAG功能，通过这样的连接，可以访问开发的FPGA或者SOC，而不需要通过传统的JTAG电缆。(Xilinx Virtual Cable (XVC) is a TCP/IP-based communication protocol that acts
like a JTAG cable and provides a means to access and debug your FPGA or SoC
design without using a physical cable. In this document are the general details
of this XVC 1.0 protocol.)
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Size: 8192 |
Author: forestmeng
|
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Description: GCU的固件，实现USB FPGA 和TCP/IP协议～(GCU firmware to implement USB, FPGA and TCP/IP protocols ~!)
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Size: 1659904 |
Author: hudieysh
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Description: 用FPGA语言，基于W5300芯片实现TCP/IP协议的网络传输，将W5300部分程序实现IP封装，只有输入输出管脚和时钟，复位等管脚(FPGA language is used to realize the network transmission of TCP/IP protocol based on W5300 chip. The W5300 part of the program realizes IP packaging, and only the input and output pins and the clock, reset and so on.)
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Size: 24583168 |
Author: 董教授 |
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Description: 用FPGA，基于M88E1111芯片实现的TCP/IP协议的千兆网，将协议封装成IP核(With the FPGA, the TCP/IP protocol based on the M88E1111 chip is used to encapsulate the protocol into IP core)
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Size: 19307520 |
Author: 董教授 |
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